Procurement for this part runs through the independent distribution channel.
15 ns speed grade — timing closure in glue logic
The 15 ns propagation delay is the combinational path limit from input to registered output through the AND/OR array. This sets the maximum system clock frequency for state machines and address decoders built with this PLD. At 5V supply, the 15 ns speed is typical for the 22V10 architecture in the CQ (commercial temperature, quarter-power) variant. The 28-PLCC J-Lead package adds about 2 ns of package delay versus the DIP version, so board-level timing budgets should account for that.
10 macrocells and EE PLD reprogrammability
Ten macrocells give 10 registered or combinatorial outputs, each configurable as registered, combinatorial, or bidirectional. This is the standard density for the 22V10 architecture — enough for medium-complexity state machines, bus interfaces, and address decoding. The EE PLD programmable type means the device is electrically erasable and reprogrammable. It supports in-system or programmer-based programming and can be erased and reused during development. No UV erasure window is needed.
28-PLCC J-Lead — footprint and rework considerations
The J-Lead package has a body size of 11.51 x 11.51 mm. J-Lead packages require a specific PLCC socket for programming or a reflow profile with a peak temperature compatible with the J-bend lead form. The footprint is standard for 28-pin PLCC and matches industry-wide socket patterns. Surface-mount mounting type with J-Leads means the part sits flush on the board with the leads tucked under the body. Visual inspection of solder joints is more difficult than with gull-wing leads; X-ray or angled inspection may be needed for production verification.