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Microchip Technology ATF22V10C-15PU — FPGA / CPLD & Programmable Logic

Microchip ATF22V10C-15PU EE PLD, 15 ns, 10 Macrocells

MPNATF22V10C-15PU
Active

Microchip ATF22V10C-15PU, EE PLD, 22V10 series, 15 ns speed, 10 macrocells, 5V input, 24-DIP (0.300", 7.62mm) through-hole package, tube.

$2.2800Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

ATF22V10C-15PU specifications
ParameterValue
Series22V10
MountingThrough Hole
Programmable typeEE PLD
Voltage - input5V
Speed15 ns
PackageTube
Case24-DIP (0.300\", 7.62mm)
Number of macrocells10

Product details

The ATF22V10C-15PU is a 5V EE PLD from Microchip's 22V10 family, offering 10 macrocells with a 15 ns propagation delay. That 15 ns tpd is the combinatorial path budget from any input through the AND-OR array to the registered or combinatorial output — at a 5V supply, it gates the maximum system clock to about 33 MHz for registered state machines, and sets the address-to-output window for decode logic. The through-hole 24-DIP package (0.300-inch body) mates with standard 0.100-inch pitch sockets or solders directly into plated through-holes on legacy or low-volume boards.

10 macrocells — sizing the logic budget

Ten macrocells, each configurable as registered or combinatorial, sum to roughly 200–300 equivalent gate-equivalents depending on the product-term sharing. For a typical address decoder, a few chip-select glues, and a small state machine, the 22V10 fits without spilling into a larger CPLD. The EE reprogrammability means the part can be re-allocated across board variants with different JEDEC files — no mask charge, no OTP lock-in.

Microchip lists the ATF22V10C-15PU as Active product status. No NRND or EOL notice applies at this writing.

Frequently asked questions

What voltage does the ATF22V10C-15PU require?

The ATF22V10C-15PU operates from a 5V supply rail.

How do I program the ATF22V10C-15PU?

The ATF22V10C-15PU is an EE PLD programmed with standard JEDEC fuse-map files. It is compatible with common PLD programmers that support the 22V10 architecture, including those from Data I/O, BP Microsystems, and Xeltek. No on-chip debug or JTAG is available — programming is done out-of-circuit on a device programmer.