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Microchip Technology ATF22V10BQL-20JC — FPGA / CPLD & Programmable Logic

ATF22V10BQL-20JC 22V10 EE PLD, 20 ns, 10 Macrocells, 28-PLCC

MPNATF22V10BQL-20JC
Obsolete

Microchip ATF22V10BQL-20JC, 22V10 series EE PLD, 20 ns propagation delay, 10 macrocells, 5V supply, 28-PLCC (J-Lead) package, surface mount.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

ATF22V10BQL-20JC specifications
ParameterValue
Series22V10
MountingSurface Mount
Programmable typeEE PLD
Voltage - input5V
Speed20 ns
PackageTube
Case28-LCC (J-Lead)
Number of macrocells10

Product details

The Microchip ATF22V10BQL-20JC is an electrically-erasable programmable logic device (EE PLD) from the 22V10 family, offering 10 macrocells and a 20 ns propagation delay. It operates from a single 5V supply and comes in a 28-PLCC (J-Lead) package, surface-mount. This class of PLD is typically used for board-level glue logic — address decoding, state machines, bus arbitration — in industrial controllers, telecom line cards, and legacy embedded systems where a small, fast, reprogrammable logic block replaces multiple 7400-series TTL parts.

20 ns speed — timing margin in a 5V system

The 20 ns propagation delay (tpd) sets the maximum clock frequency for registered logic at roughly 50 MHz in a typical synchronous design. For combinatorial paths, the 20 ns window includes input-to-output delay through the AND-OR array and macrocell; a system with a 25 MHz clock has 40 ns of cycle time, leaving 20 ns of margin after the PLD delay for trace and buffer delays. That margin shrinks fast if the design uses cascaded PLDs or long board traces.

10 macrocells — logic capacity for moderate consolidation

Ten macrocells, each with a programmable flip-flop (D/T/JK) and output polarity, can absorb roughly 20–30 SSI/MSI logic gates worth of combinatorial and registered functions. Typical applications include a 3-to-8 decoder with registered outputs, a 4-bit counter with load and clear, or a simple state machine with 8–10 states. Designs that exceed 10 macrocells or need more than 20–30 product terms per output will overflow this device.

28-PLCC J-Lead — board footprint and rework

The 28-PLCC package (11.51 x 11.51 mm body) uses J-leads formed under the body, requiring a solder pad pattern with a central thermal pad (typically connected to ground) and a 1.27 mm pitch. The J-lead profile is less prone to tombstoning than gull-wing, but inspection of the solder joint under the package requires X-ray or a side-view scope. Rework with hot air is straightforward — the PLCC body lifts cleanly when the solder reflows, and the pads are robust to a few removal cycles.

Frequently asked questions

What is the replacement for ATF22V10BQL-20JC?

The 22V10 architecture is broadly second-sourced; a pin-compatible alternative from another manufacturer (e.g., Lattice GAL22V10 or Cypress PLDC22V10) may fit, but verify the programming algorithm and JEDEC fuse map compatibility before substituting.

What is the speed of the ATF22V10BQL-20JC?

The ATF22V10BQL-20JC has a 20 ns propagation delay (tpd), which supports registered clock frequencies up to approximately 50 MHz in typical synchronous designs.