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Microchip Technology ATF16V8BQL-15JC — FPGA / CPLD & Programmable Logic

ATF16V8BQL-15JC EE PLD, 8 Macrocells, 15 ns, 20-PLCC

MPNATF16V8BQL-15JC
Obsolete

Microchip ATF16V8BQL-15JC, EE PLD, 16V8 Series, 8 Macrocells, 15 ns, 5V, 20-PLCC (J-Lead), Surface Mount, Tube

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

ATF16V8BQL-15JC specifications
ParameterValue
Series16V8
MountingSurface Mount
Programmable typeEE PLD
Voltage - input5V
Speed15 ns
PackageTube
Case20-LCC (J-Lead)
Number of macrocells8

Product details

EE PLD with 8 macrocells — confirming the BOM match

The Microchip ATF16V8BQL-15JC is an electrically-erasable programmable logic device (EE PLD) from the 16V8 series, offering eight macrocells in a 20-lead PLCC package with J-leads for surface-mount assembly. It operates from a single 5V supply and is specified with a 15 ns propagation delay, which sets the timing budget for glue-logic replacement, address decoding, or state-machine integration in legacy 5V systems.

15 ns speed — what it buys on the bus

The 15 ns propagation delay means the PLD can handle combinatorial logic paths up to about 66 MHz in a typical 5V TTL environment, assuming reasonable fan-out and board parasitics. This is the figure that determines whether the part can meet setup-and-hold margins in a given address decode or chip-select path.

Microchip lists the ATF16V8BQL-15JC as Obsolete. Availability is through independent distribution and surplus inventory channels.

Package and footprint — PLCC-20 J-Lead

The 20-PLCC package (9x9 mm body) with J-leads is a surface-mount form factor distinct from the DIP or TQFP alternatives in the 16V8 family. The J-lead footprint requires a specific PLCC socket or a solder-paste stencil designed for the 1.27 mm pitch gull-wing profile.

Frequently asked questions

What is the replacement for the ATF16V8BQL-15JC?

A functionally similar device would be another 16V8-series EE PLD from Microchip, but pin compatibility and timing must be verified against the specific BOM requirement.