Active 4Kbit I²C EEPROM — BOM-fit for low-voltage serial storage
The 34AA04-I/ST is a 4Kbit serial EEPROM from Microchip Technology, organized as 256 x 8 x 2 banks, communicating over an I²C bus at up to 1 MHz.
350 ns access, 5 ms page write — timing for the firmware engineer
Read access time is 350 ns — the time from the I²C address byte ACK to the first data bit appearing on SDA. At a 1 MHz bus clock, each bit takes 1 µs, so the access time adds less than one clock cycle of latency. The write cycle time for a page or word is 5 ms — budget this into the firmware write routine; polling the ACK after each write command avoids bus hangs. The part retains data across this band without read-disturb issues common in flash, making it suitable for calibration constants or boot parameters that must survive a cold start.
8-TSSOP footprint — layout and supply routing
The 34AA04-I/ST comes in an 8-TSSOP package — 0.65 mm pitch, 4.4 mm body width, 3.0 mm body length. The surface-mount footprint is standard for this package family; the narrow pitch keeps board area under 15 mm². Supply decoupling: a 100 nF ceramic cap within 5 mm of pins 4 (VSS) and 8 (VCC) is sufficient given the 1.7V–3.6V range and typical active current under 1 mA. The I²C bus lines (SCL, SDA) are open-drain — pull-up resistors to VCC are required. At 1 MHz bus speed, the RC time constant of the pull-up and bus capacitance limits the maximum trace length; keep the total bus capacitance below 400 pF per the I²C specification for fast mode.
Second-source cross-reference — AT24C08D-SSHM-B
The AT24C08D-SSHM-B is a functional second-source candidate — same I²C interface, same 1 MHz clock, same 8-TSSOP package, same 1.7V supply minimum, and same industrial temperature range. The key difference: the AT24C08D is 8Kbit (double the density) organized as 1K x 8, while the 34AA04 is 4Kbit organized as 256 x 8 x 2. If your BOM uses only the lower 4Kbit address space and the upper address bits are don't-cares, the AT24C08D can drop in without a firmware change — the I²C device address is set by the A0/A1/A2 pins, which are pin-compatible.