32 macrocells at 1.8 V — the low-power CPLD for glue logic
The LC4032ZC-75TN48C is a 32-macrocell CPLD from Lattice's ispMACH 4000Z family, running on a 1.7 V to 1.9 V core supply. With a pin-to-pin propagation delay of 7.5 ns max, it handles address decoding, bus bridging, and state-machine tasks where the timing budget is tight but the power rail is already 1.8 V.
I/O count and package — 32 pins in a 7x7 mm TQFP
The supplier device package is 48-TQFP (7x7). Surface-mount assembly is standard; the fine pitch calls for a controlled solder-paste stencil and a reflow profile matching the JEDEC MSL level on the reel label.
Temperature grade and compliance
Rated for 0°C to 90°C junction temperature — a commercial-grade window that covers most indoor equipment, telecom racks, and benchtop instruments.