32-macrocell CPLD with 7.5 ns pin-to-pin delay
The LC4032V-75TN48C is a Lattice ispMACH 4000V CPLD packing 32 macrocells in a 48-TQFP package. The 7.5 ns propagation delay (tpd1 max) means combinatorial logic paths close within one 133 MHz clock cycle — fast enough for address decoding, bus bridging, or glue logic in a 100 MHz system without extra pipeline stages. 32 user I/O are available on the 48-pin LQFP, leaving 16 pins for supply, ground, and JTAG.
Temperature grade and package fit
Rated for 0°C to 90°C junction temperature — this is the commercial-temperature band. The 48-TQFP (7x7 mm body) with 0.5 mm pitch is a standard footprint; the exposed pad is not present on this package, so thermal relief is through the leadframe only. Surface-mount assembly with standard reflow profiles works for this MSL level (not stated, but typical for Lattice TQFP). In-system programmable via JTAG — no socket or UV eraser needed. The 32 macrocells are organized into two logic blocks, each feeding a PAL-like product-term array. For a 16-bit address decoder or a small state machine, this density leaves headroom for a few extra registered outputs.