ICE40UL1K-CM36AITR1K
Lattice Semiconductor Corporation
MOQ 1 · Tape & Reel (TR) · RoHS · EIA-481 · DAP/DDP · T/T
Technical specifications
| Parameter / Attribute | Specification / Value |
|---|---|
| Series | iCE40 UltraLite™ |
| Mounting | Surface Mount |
| Supply voltage | 1.14V ~ 1.26V |
| Operating temperature | -40°C ~ 100°C (TJ) |
| Package | Tape & Reel (TR) |
| Number of i (O) | 26 |
| Case | 36-VFBGA |
| Total RAM bits | 57344 |
| Number of LABs (CLBs) | 156 |
| Number of logic elements (Cells) | 1248 |
Need Stock or a Drop-in Second-Source for ICE40UL1K-CM36AITR1K?
Package: QFN / ucBGA / WLCSP / TQFP · Pin-compatible replacements with immediate Shenzhen spot stock
The iCE40 line is the FPGA family that the hobby and small-batch world actually uses - and the data says the same thing about buyers: searches concentrate on Lattice CPLD and iCE40 class parts while Xilinx orderables sit at the noise floor. The family is five sub-splits with wildly different capabilities (UltraLite to UltraPlus) sharing a naming theme and a common trait: an SRAM fabric that must be loaded at every power-up - from an external SPI flash, a host CPU, or the family-internal NVCM. The sourcing consequence is structural: an iCE40 socket is never just an FPGA line on the BOM; it is a two-part relationship with a configuration memory.
Verified Pin-Compatible Replacements (3 verified alternatives)
The UltraPlus Flagship
Shenzhen Spot Stock (24-48h Dispatch)
The richest sub-split: 5,280 LUTs with 1Mb of SPRAM (four 256kb blocks), DSP blocks, two hardened SPI and two I2C blocks, and on-chip oscillators - built for always-on sensor buffering and audio pre-processing.
Low-power single-rail design point; the UltraPlus is the part behind most current iCE40 designs.
The Performance Sub-Split
Shenzhen Spot Stock (24-48h Dispatch)
The HX line trades standby current for more logic per die (HX1K/4K/8K against LP1K/4K/8K); the classic hobby board part of the iCE40 generation.
Low-power but not the micropower LP class; check the static current against the design budget.
The Step-Up Platform
Shenzhen Spot Stock (24-48h Dispatch)
The next class above iCE40 in the Lattice stack: higher logic density and hardened high-speed interfaces for video, networking and instrumentation designs.
Multi-rail FPGA supply design - not a drop-in to any iCE40 socket.
Buyer & Quality Checklist for Sourcing Alternatives
- Every iCE40 is SRAM-based: the design lives in configuration memory loaded at power-up (external SPI flash, host controller, or NVCM where present). A board without its config flash is a board with a blank FPGA - when sourcing iCE40, source the paired W25Q-class flash on the same order.
- The five sub-splits (UltraLite / LP / HX / Ultra / UltraPlus) are different devices, not grades of one device: logic, memory, DSP and hardened IP differ, and the same-size package does not imply the same pin map.
- Small packages drop features: several mini outlines have no PLL, and the constant-current LED sink exists on selected packages only. The package letter in the orderable number is a spec, not a shipping choice.
- NVCM configurations are instant-on and secure but one-shot - production planning for NVCM-programmed devices needs lead time and programming decisions upstream, not at the bench.
- The market leans Lattice for this class (buyer searches concentrate here, not on Xilinx orderables): keep depth in iCE40 and the config flash, with ECP5 quoted case-by-case.
- iCE40 boards in the repair channel are numerous (hobby, education, instrumentation): the two failure parts are the FPGA and its config flash - check the flash first, it is cheaper and it holds the bitstream.
Frequently Asked Technical Questions
Q: Which iCE40 sub-family do I need?
A: Choose by need: UltraPlus (UP5K) when on-chip SPRAM or DSP is required; HX/LP for general low-power logic with more density; Ultra for mobile glue logic with hardened SPI/I2C; UltraLite for the absolute smallest always-on designs. Sub-splits are not interchangeable.
Q: Does iCE40 need an external flash chip?
A: It configures at every power-up: from an external SPI flash in self-boot mode, from a host CPU in slave mode, or from the internal NVCM where the design was programmed there. Most boards carry a small W25Q-class SPI flash for the bitstream - source it with the FPGA.
Q: Can I replace a dead iCE40 with an ECP5?
A: No - different family, different packaging and supply design. ECP5 is the step-up platform for higher density and interfaces; migrating is a re-layout and re-synthesis project.