Altera MAX® 7000S CPLD, EPM7160SLC84-6, 160 macrocells, 64 I/O, 6 ns pin-to-pin delay, 5 V supply, 84-PLCC, commercial temperature.
| Parameter / Attribute | Specification / Value |
|---|---|
| Series | MAX® 7000S |
| Mounting | Surface Mount |
| Programmable type | EE PLD |
| Voltage supply - internal | 4.75V ~ 5.25V |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Bulk |
| Number of i (O) | 64 |
| Case | 84-LCC (J-Lead) |
| Number of gates | 3200 |
| Number of macrocells | 160 |
| Delay time tpd(1) max | 6 ns |
| Number of logic elements (Blocks) | 10 |
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The Altera EPM7160SLC84-6 is a MAX® 7000S-series EE PLD with 160 macrocells and 64 I/O lines.
The 6 ns propagation delay determines whether the CPLD can decode addresses or route control signals fast enough for the bus.
The internal supply voltage range is 4.75 V to 5.25 V — a standard 5 V rail.
It has 160 macrocells and 64 I/O lines.
The maximum pin-to-pin delay (tpd) is 6 ns.