7.5 ns tpd — timing budget for the bus
The 7.5 ns propagation delay is the key timing parameter: it defines the maximum combinatorial path the CPLD can absorb without slowing down the system clock. For a 100 MHz bus, that leaves about 2.5 ns of margin after setup/hold on the receiving flop — enough for a few levels of LUT-based decode. If your design needs faster combinatorial throughput, the MAX II EPM240F100C5N offers 4.7 ns tpd but in a different density and package (192 macrocells, 100-pin TQFP).
Sourcing and supply
The EPM7128AEUC169-7 is an active, current-production part from Intel/Altera.