120 MHz PLL frequency multiplier in 16-SOIC
The W532GI is a PLL-based frequency multiplier from Infineon Technologies, accepting a clock or crystal input and delivering a single-ended CMOS output up to 120 MHz. It operates from either a 3.0 V–3.6 V or a 4.5 V–5.5 V supply rail, making it drop-in compatible with both 3.3 V and 5 V logic domains without an intermediate regulator.
Single-ended output, no differential — design-in check
Both input and output are single-ended CMOS — the part does not support differential signalling. For LVDS or LVPECL clock trees, this part is not a fit. The 1:1 input-to-output ratio means one reference in, one clock out; it multiplies frequency but does not fan out to multiple loads. The 16-SOIC package (7.50 mm body width) is a common footprint; the 0.295-inch row spacing matches standard SOIC land patterns.
Active production — no obsolescence risk
RoHS non-compliant — verify your assembly house's exemption allowance if your BOM requires full RoHS conformance.
