PLL-based clock fanout for 3.3V logic
The Cypress W162-09GT is a PLL-based zero delay buffer that regenerates an input clock with deterministic phase alignment, delivering up to 133 MHz on nine outputs from a single input (3:9 ratio). It operates from a 2.97V to 3.63V supply, matching standard 3.3V logic rails, and is packaged in a narrow 16-SOIC (0.154" body width) for surface-mount assembly.
The 133 MHz maximum frequency covers most common system clocks — PCI Express reference clocks, Ethernet MAC/PHY interfaces, and general-purpose processor or FPGA clock trees. The 3:9 input-to-output ratio means you can feed up to three separate input clocks (or one clock with three fanout branches) and get nine total outputs, which is enough to drive multiple loads without adding external fanout buffers. The non-differential I/O (No/No) tells you this part is for single-ended clock signals, not LVDS or LVPECL.
Supply and temperature — where it fits
The 2.97V to 3.63V supply range is a standard 3.3V ±10% window, so the part runs directly from a 3.3V rail without an extra regulator. If your design needs extended temperature, you would look at the industrial-grade variant in this family.