16-SOIC PLL buffer with 1:8 fanout
The W152-12G: It accepts a single-ended input and distributes it to eight outputs at a maximum frequency of 140 MHz. The 1:8 ratio means this device replaces a discrete clock fanout tree for up to eight loads, saving board area and reducing skew between branches. The PLL locks the output phase to the input, so downstream devices see aligned clock edges without external delay matching.
Board-fit and supply rails
The 16-SOIC footprint (3.90 mm body width) is a common industry standard — the same land pattern serves many clock buffers and logic devices, so no custom footprint is needed.
Sourced through independent distribution channels. No stock-holding claim is made; each order is quoted individually.
Parametric notes for the BOM engineer
Single-circuit design with a non-differential input and output — this is a single-ended clock buffer, not a differential (LVDS/LVPECL) fanout. If your clock source is differential, a single-ended translator or a different buffer family is needed ahead of this part. The device includes a divider (Yes) but no multiplier (No). This means the output frequency is either the input frequency or a divided-down version — it cannot generate a higher-frequency clock from a lower-frequency reference without an external PLL or oscillator.