Clock distribution for spread-spectrum systems
The W132-10BX is a PLL-based zero delay buffer from Infineon's Spread Aware™ family, designed to cleanly fan out a single clock input to eleven LVCMOS or LVTTL outputs while preserving the spread-spectrum profile of the incoming clock. It operates from a 2.97 V to 3.63 V supply and supports clock frequencies up to 140 MHz, making it suitable for PCIe reference clocks, Ethernet PHY timing, or general-purpose board-level clock trees that need low-jitter distribution.
Fan-out and frequency ceiling
With a 2:11 input-to-output ratio, one input can be used as a feedback path for zero-delay alignment, leaving ten dedicated outputs to drive multiple loads — enough for a typical networking or compute blade clock tree. The 140 MHz maximum frequency covers most 100 MHz and 125 MHz reference clocks, but not 156.25 MHz or higher SERDES rates — confirm your target frequency against this ceiling before committing the BOM.
Active production, RoHS non-compliant
Note that this part is RoHS non-compliant.
Package and temperature grade
Housed in a 24-TSSOP (4.40 mm width) surface-mount package, the footprint is standard for this pin count — layout guidelines from the TSSOP-24 land pattern apply. It is not specified for industrial or automotive environments; if your system sees -40°C or +85°C, you need a different temperature-grade part.