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Infineon Technologies S29GL256S10DHIV20 — Logic ICs

S29GL256S10DHIV20 256 Mbit Parallel NOR Flash, 100 ns

MPNS29GL256S10DHIV20
End of Life

Infineon GL-S series, S29GL256S10DHIV20, 256 Mbit parallel NOR flash, 100 ns access time, 1.65V-3.6V supply, 64-FBGA (9x9), -40°C to 85°C.

$7.78Ref. price · indicative, final on quote
Packaging64-LBGA
RoHSROHS3 Compliant
SeriesGL-S
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

S29GL256S10DHIV20 specifications
ParameterValue
SeriesGL-S
Memory typeNon-Volatile
MountingSurface Mount
Supply voltage1.65V ~ 3.6V
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageTray
TechnologyFLASH - NOR
Access time100 ns
Memory size256Mbit
Memory formatFLASH
Case64-LBGA
Memory organization16M x 16
Write cycle time - word, page60ns

Product details

256 Mbit parallel NOR flash for code shadowing and data logging

The Infineon S29GL256S10DHIV20 is a 256 Mbit parallel NOR flash memory from the GL-S series, organized as 16M x 16 bits. It provides a 100 ns access time over a wide supply range of 1.65V to 3.6V, making it suitable for both legacy 1.8V and 3.3V system buses. The 60 ns write cycle time (word/page) supports efficient firmware updates and data logging in embedded systems. Packaged in a 64-FBGA (9x9 mm), it is intended for surface-mount assembly on industrial and telecom PCBs where reliable, long-life code storage is required.

100 ns access time — bus timing margin

For a host controller running at 50 MHz (20 ns cycle), this means the flash needs about five clock cycles before the first read data appears. Compared to the 512 Mbit GL-T sibling (S29GL512T11TFIV20) with a 110 ns access time, this part offers a 10 ns faster read path — a meaningful margin when the memory bus is shared with other peripherals or when the controller's chip-select-to-output timing is tight.

The 64-FBGA (9x9 mm) package has a 0.8 mm ball pitch typical of this density class.

Frequently asked questions

Will S29GL256S10DHIV20 drop into a board designed for S29GL512T11TFIV20?

Both parts share the same 64-FBGA footprint and parallel interface, but the 512 Mbit sibling has a 110 ns access time versus 100 ns here. The density difference (256 Mbit vs 512 Mbit) means the memory map and software must be reconfigured. The package is a drop-in fit; the system timing and firmware are not.