256Mbit parallel NOR Flash, 90 ns access
The S29GL256P90TFIR13 is a 256Mbit parallel NOR Flash from Infineon's GL-P series, organized as 32M x 8 bits. The 90 ns access time sets the random-read latency ceiling — the controller must insert wait states on a bus clock faster than ~11 MHz unless the chip is in page or burst mode.
Timing and bus interface
The parallel interface uses a multiplexed address/data bus — 8-bit data width at the I/O pins, with the address latched on the falling edge of CE# or WE#. The 90 ns access time applies to the initial random read; subsequent sequential reads within the same page benefit from the page-mode access, which is faster but not specified in this listing. Write cycle time per word or page is also 90 ns, meaning the device can sustain a programming throughput of roughly 1.1 MB/s in a page-write sequence, assuming the controller meets the timing for the command sequence and polling.
It is ROHS3 compliant, with no lead, mercury, cadmium, or restricted phthalates per the EU RoHS directive.
Package and board integration
Surface-mount 56-TSOP, 0.724" body width (18.40 mm), with a standard 0.50 mm pin pitch. The package is a thin small-outline profile — the seated height is approximately 1.0 mm, suitable for mezzanine or stacked-board assemblies where clearance is tight. Available in Tape & Reel (TR) and Cut Tape (CT) options. The TR quantity is typically 1,000 pieces per reel for this package size; CT is for smaller prototype or repair quantities.