133 MHz Quad I/O — what it buys the firmware engineer
Quad-SPI at 133 MHz pushes the raw read throughput past 66 MB/s in quad-output mode. For a Cortex-M or RISC-V booting from this NOR, that means the firmware shadow from the 512 Mbit array into the MCU's internal SRAM completes in well under a second — no need for a dedicated parallel Flash bus. The Quad I/O interface uses the same four data pins for address and data, so the layout stays at six signals (CS, SCK, IO0–IO3) plus supply and ground.
The 16-SOIC (7.50 mm width) footprint is a common NOR Flash land pattern — double-check the pin 1 orientation against your board, but the 300-mil body is standard across the FL-S family.
The FL-S series has broad second-source overlap with other 512 Mbit Quad-SPI NOR parts, but Infineon's own die revision and command set should be verified against your host controller's SPI timing.