512 Mbit NOR Flash for automotive and industrial code storage
It stores firmware, calibration maps, and boot code in engine control units, ADAS modules, and telematics boxes where non-volatile retention and fast read are required. The Quad I/O interface delivers sustained throughput at a 133 MHz clock, cutting code-shadowing time compared to standard SPI.
The 133 MHz SPI clock with Quad I/O (four data lines) gives a theoretical peak of 532 Mbps. In practice, the read latency and command overhead mean the sustained throughput is lower, but it still beats dual SPI hands-down for booting a high-end MCU or FPGA configuration memory.
Package and footprint: 16-SOIC (300 mil wide)
It is a surface-mount, non-leaded package that reflows with standard Pb-free profiles. The Tray shipping medium is common for volume production, but reel options exist through the family. No exposed pad — thermal dissipation is through the leads, so keep trace widths adequate for continuous read bursts.