256 Mbit SPI NOR Flash for code shadowing and data logging
It uses a Quad I/O SPI interface running at up to 66 MHz, which gives a practical read throughput edge over standard SPI without adding pins.
66 MHz Quad I/O — what it means for boot time and OTA updates
The 66 MHz clock rate with Quad I/O mode lets the host controller read four bits per cycle, which roughly quadruples the sustained throughput compared to single-bit SPI at the same frequency. For a 256 Mbit part, this matters most during firmware shadowing from Flash to RAM at power-up and during over-the-air update windows where the bus is busy. The SPI interface keeps the pin count low — only six signals for the Quad I/O — which simplifies the PCB routing and frees GPIOs on the MCU.
Active lifecycle and supply continuity
The FL-S series is a mature, widely deployed NOR Flash family with a long market history, which supports multi-year supply planning.
Package and footprint — 16-SOIC wide-body
The surface-mount SOIC footprint is standard for reflow assembly and hand-solder rework, and the wide-body variant gives better clearance for routing under the package.