256 Mbit NOR Flash with Quad-SPI — what the 133 MHz clock buys you
Its SPI and Quad I/O interface clocks at 133 MHz, which translates to a sustained read throughput high enough to feed a Cortex-M7 or RISC-V core directly from flash without a DRAM cache — provided the controller's Quad-SPI peripheral can match the rate.
Package and footprint — 8-WSON with exposed pad
Housed in an 8-WDFN exposed pad package (supplier device package 8-WSON, 6x8 mm), this part is a surface-mount device that needs a thermal pad via stitch under the exposed pad to keep junction temperatures in check during continuous burst reads.
The FL-S series has a broad installed base, and Cypress (now Infineon) continues to support it with datasheets, application notes, and PCN notifications.