256 Mbit SPI NOR Flash with Quad I/O — fit for code-shadow and data logging
It uses a Quad I/O SPI interface that delivers read throughput up to 133 MHz clock rate, suitable for execute-in-place (XIP) firmware, boot code shadowing, and data logging in industrial and telecom equipment. The 2.7V to 3.6V supply range matches 3.3V logic families directly, so no level shifters are needed on the SPI bus.
For production builds with multi-year horizon, this means no imminent last-time-buy or end-of-life notice.
Industrial temperature grade and 16-SOIC footprint
At 133 MHz, the Quad I/O interface delivers a theoretical peak read rate of 532 Mbps (four data lines × 133 MHz). For real-world firmware reads, the controller must support Quad I/O commands (1-4-4 or 4-4-4 protocol). The 256 Mbit density provides 32 MB of non-volatile storage, enough for a full application image plus a fallback recovery partition in many embedded designs. The 2.7V minimum supply ensures operation through the lower end of a 3.3V rail with typical ±5% tolerance.