256 Mbit NOR Flash with Quad-SPI at 133 MHz
It communicates over a SPI interface with Quad I/O support, clocked at 133 MHz. That clock rate, combined with the Quad I/O mode, delivers a sustained read throughput that keeps a Cortex-M or RISC-V core fed for execute-in-place (XIP) code shadowing without wait-state bottlenecks.
Quad I/O read performance – what the 133 MHz clock buys
At 133 MHz in Quad I/O mode, the S25FL256SAGBHIB03 can deliver around 66 MB/s sustained read throughput (133 MHz × 4 bits per cycle). That is enough to support real-time audio buffers, display frame buffers, or OTA staging without external DRAM. The SPI bus also keeps pin count low — only six signals (CLK, CS, IO0–IO3) — which simplifies layout on dense PCBs.
The FL-S series has broad second-source overlap with other Quad-SPI NOR parts, but the active status means you are not forced to exercise that option yet.
24-BGA footprint – layout notes
Housed in a 24-ball BGA measuring 6 mm x 8 mm (ball pitch 0.8 mm), this package fits on a two-layer board if the escape routing uses via-in-pad or dogbone fanout. The 0.8 mm pitch is manageable with standard PCB fabrication tolerances. Decoupling: a 100 nF ceramic within 2 mm of each supply ball pair, plus a 4.7 µF bulk cap near the BGA cluster, keeps the supply clean during page-program bursts.