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Infineon Technologies S25FL256LAGMFB000 — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon S25FL256LAGMFB000 NOR Flash, 256 Mbit, 133 MHz

MPNS25FL256LAGMFB000
End of Life

Infineon S25FL256LAGMFB000, Automotive AEC-Q100 FL-L series, 256 Mbit NOR Flash, 133 MHz SPI Quad I/O / QPI, 2.7-3.6 V, 32M x 8, -40 to 105 °C, 16-SOIC (7.50 mm), tray.

$5.5288Ref. price · indicative, final on quote
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

S25FL256LAGMFB000 specifications
ParameterValue
SeriesAutomotive, AEC-Q100, FL-L
Memory typeNon-Volatile
MountingSurface Mount
Voltage2.7V ~ 3.6V
Frequency133 MHz
Memory interfaceSPI - Quad I/O, QPI
Operating temperature-40°C ~ 105°C (TA)
PackageTray
TechnologyFLASH - NOR
Memory size256Mbit
Memory formatFLASH
Case16-SOIC (0.295\", 7.50mm Width)
Memory organization32M x 8

Product details

256 Mbit NOR flash for automotive code storage

The S25FL256LAGMFB000 is a 256 Mbit NOR flash from Infineon's FL-L series, organized as 32M × 8 bits and accessed over an SPI Quad I/O or QPI interface at up to 133 MHz. This density suits code-shadowing for a single-core MCU boot image or a moderate-size data-logging buffer in an automotive ECU. AEC-Q100 Grade 1 qualification means the device is characterized and guaranteed over the -40 to +105 °C ambient temperature range — the full under-hood and cabin thermal envelope for passenger vehicles and light trucks. The 2.7-3.6 V supply rail matches the common 3.3 V automotive power domain without an external regulator.

What the 133 MHz Quad I/O bus means for throughput

The SPI Quad I/O interface at 133 MHz delivers a theoretical peak read throughput of 532 Mbit/s (four data lines × 133 MHz). In practice, the sustained rate depends on the command overhead and the initial access latency, but this clock speed puts the device in the high-performance tier for NOR flash — fast enough to support execute-in-place (XIP) for a real-time boot sequence without copying the image to RAM first. The QPI (Quad Peripheral Interface) mode reduces the command byte to a single serial cycle, cutting protocol overhead on short random reads. For a firmware-over-the-air (FOTA) update routine that reads many small sectors, QPI can improve effective throughput by 15-25 % compared to standard Quad I/O command sequences.

This NOR flash is suitable for both new design-ins and production replenishment without a looming obsolescence risk.

Frequently asked questions

Does the 133 MHz clock rating support a 120 MHz ECU host with Quad I/O?

133 MHz maximum clock gives 13 MHz of headroom over a 120 MHz host — 10.8% margin, which is adequate for Quad I/O read cycles. Whether the host flash controller's hold-time and setup-time budget at 120 MHz requires firmware adjustment is a characterization item specific to your MCU, not a spec gap in the device itself.