128 Mbit NOR Flash with Quad-SPI — active, no LTB risk
It communicates over a Quad I/O SPI interface at up to 80 MHz, giving a practical read throughput around 40 MB/s in Quad mode — enough for XIP (execute-in-place) boot from most MCU Quad-SPI controllers.
The 80 MHz clock is the ceiling for Quad I/O reads. At that speed, the SPI bus delivers roughly 40 MB/s, which keeps a Cortex-M4 or M7 fed without waiting on flash wait states. The Quad I/O interface also means only six signal pins (CS, CLK, IO0–IO3) are needed, saving board area versus a parallel NOR. The 2.7 V minimum supply means the flash stays alive through a 3.3 V rail that dips during brownout or cold-crank.
Package and footprint — 8-WSON with exposed pad
The 8-pin footprint is shared with other FL-S density options, so a layout for the 128 Mbit part can also accept 256 Mbit or 512 Mbit siblings without a board spin.