80 MHz Quad I/O — bus margin and throughput
At 80 MHz with Quad I/O, the part reads at an effective bit rate of 320 Mbps. That is enough to shadow a firmware image into SRAM in under a second or stream configuration tables without stalling the host. The SPI interface keeps pin count low — four data lines plus clock and chip select — which simplifies PCB routing on dense boards. The 80 MHz rating is the maximum clock; actual throughput depends on the host controller's Quad-SPI peripheral and the command overhead (fast read with 4-byte address).
Package and thermal — 8-WSON with exposed pad
The part comes in an 8-WDFN exposed-pad package, supplier device package 8-WSON (6x8 mm). The 8-WSON footprint is shared across several FL-S density variants, so a single board layout can accommodate 64 Mbit through 256 Mbit parts with minor BOM changes.