128 Mbit NOR Flash with a 133 MHz Quad SPI bus
It speaks SPI with Quad I/O at up to 133 MHz — a common interface for code shadowing (execute-in-place or XIP) and firmware storage in embedded systems.
Quad SPI at speed — what the 133 MHz clock buys you
The Quad I/O interface lets four data lines run in parallel, so the effective throughput at 133 MHz is roughly 66 MB/s (133 MHz × 4 bits per clock, double-data-rate not assumed). That is fast enough to feed a high-res display frame buffer or stream firmware updates without stalling the host MCU. The 128 Mbit density holds about 16 MB of code or data — typical for a bootloader plus a moderate-size application image in an industrial controller.
Package and footprint — the 16-SOIC wide body
The 16-SOIC package has a 7.50 mm body width (the 'wide' SOIC-16), not the 3.90 mm narrow variant. If your existing layout uses a narrow SOIC-16 footprint, this part will not fit without a pad-pattern change.