128 Mbit NOR Flash with Quad-SPI for code shadowing
It uses a SPI interface with Quad I/O support, pushing the read clock to 133 MHz while keeping the pin count to a 16-SOIC footprint. The 16M x 8 organization maps cleanly to a 16 MB address space, sized for a single firmware image plus a small OTA staging area on a mid-range MCU or FPGA design.
At 133 MHz in Quad I/O mode, the part delivers a sustained read throughput around 66 MB/s (assuming a 50% duty cycle on the clock and one dummy cycle). That is enough to feed a Cortex-M7 or a mid-range FPGA configuration controller without stalling the core.
Infineon lists the S25FL128SAGMFV011 as Active. The FL-S series is a current-production family with broad distribution coverage. For dual-sourcing resilience, the pin-compatible S25FL128SAGMFI013 (same density, industrial temp, different package code) or the S25FL128SAGBHV013 (BGA package) are alternative order codes on the same die — qualify the footprint that matches your board.