Active production — AEC-Q100 Grade 1 qualified
The S25FL128SAGMFM003: AEC-Q100 Grade 1 qualification means the device is characterized and reliability-tested across the full -40 to 125 °C ambient range — the temperature band that covers underhood and engine-compartment ECUs. An OEM auditor reviewing PPAP documentation will find the grade-1 temperature classification on the qualification report.
128 Mbit density, 133 MHz SPI Quad I/O
Organized as 16 M x 8 bits, the 128 Mbit density is sized for code shadowing or data logging in automotive gateways, ADAS domain controllers, and telematic control units — enough for a full application image plus a small file system. The SPI Quad I/O interface clocks at 133 MHz, delivering a read throughput of 532 Mbit/s in quad mode — fast enough to support XiP (execute-in-place) from the NOR flash without a separate DRAM cache for boot code. The wide-body 16-SOIC (0.295-inch body width) footprint is a common JEDEC outline — no special land pattern or via-in-pad is required, and the package is reflow-compatible with standard lead-free profiles.
The part is delivered in tape-and-reel packaging, suitable for automated pick-and-place assembly. The FL-S series is Infineon's own core product line — if a BOM hedge is required, a functional equivalent from the same family would require a different order code and qualification re-run.