128 Mbit NOR Flash with Quad-SPI for embedded code and data storage
The S25FL128SAGMFB001: It communicates over a Quad I/O SPI interface at up to 133 MHz, giving read throughput that keeps a Cortex-M or RISC-V core fed for execute-in-place (XIP) or shadow-to-RAM boot.
133 MHz Quad-SPI — what it means for read bandwidth
At 133 MHz in Quad I/O mode, each clock cycle transfers four bits. The SPI interface keeps pin count to six or eight signals versus the 40+ needed for a parallel NOR.
Cypress lists the S25FL128SAGMFB001 as Active. For dual-sourcing resilience, the FL-S family includes multiple density and package variants that share the same SPI command set, so a firmware port across siblings is straightforward.
If you need a reel or tube quantity, the package code (MFB001) identifies the tube variant; the tape-and-reel suffix differs, so confirm the packing format when you request a quote.