128 Mbit NOR Flash for code shadowing and data logging
It uses a standard SPI interface running at up to 104 MHz, which gives enough read throughput for execute-in-place (XIP) booting of a microcontroller or FPGA configuration store.
That means no further production runs are scheduled, and the only available inventory is what distributors and independent suppliers hold. If your design already uses this exact code, you have two paths: buy enough for the remaining production run (last-time-buy quantities can be quoted against an RFQ), or qualify a drop-in replacement. The FL-P series has been superseded by newer families — check the S25FL128S or S25FL-L series for a pin-compatible SPI NOR Flash with the same 128 Mbit density and 104 MHz clock.
8-WSON exposed pad — layout checklist
Without that via stitch, the junction temperature rises faster during continuous read bursts, especially at 104 MHz.
SPI interface — firmware bring-up notes
At 104 MHz the SPI clock period is about 9.6 ns. The flash supports fast-read (0x0B command) with a dummy byte for the initial latency, and the 3 ms page write time means a 256-byte page takes 3 ms to program. If you are booting from this flash, the SPI controller on your MCU needs to handle the read command sequence and the dummy cycle. The write cycle time is specified per word or page — for a full-chip erase, budget roughly 64 seconds based on the 128 Mbit density and typical sector erase times for this process node.