Automotive NOR Flash for code shadowing and data logging
The SPI interface supports Quad I/O and QPI modes, enabling read throughput up to 66 MHz clock frequency. This part is intended for automotive ECU firmware storage, boot code shadowing, and data logging where non-volatile retention and fast random access are required.
Quad SPI throughput and bus margin
At 66 MHz in Quad I/O mode, the effective read bandwidth reaches roughly 33 MB/s — enough to support XIP (eXecute-In-Place) for many real-time kernels without a separate RAM shadow. The QPI mode reduces command overhead by using the same four I/O lines for address and data, which tightens the first-read latency. For a design targeting fast boot under 500 ms from power-on, this part's 66 MHz clock and Quad interface keep the bus margin comfortable.
AEC-Q100 grade and temperature range
No PPAP letter is included in this listing, but the AEC-Q100 marking on the device itself is the usual evidence for production release.
Supplied in a 16-pin SOIC wide-body (7.50 mm width) package, surface-mount. The 0.295-inch body width matches the standard JEDEC SOIC-16W footprint. No exposed thermal pad — power dissipation is modest for a NOR Flash device. MSL rating is not listed here; assume MSL 3 unless a bake step is confirmed from the reel label.