128 Mbit NOR Flash with Quad-SPI — what the specs mean for your design
It uses a standard SPI interface with Quad I/O and QPI support, clocked at 133 MHz.
133 MHz clock and Quad I/O — read throughput and bus timing
At 133 MHz with Quad I/O, the part delivers a sustained read throughput that keeps the CPU fed during XIP execution or OTA staging. The QPI mode reduces the instruction overhead by using a 4-bit address/command, which tightens the bus turnaround. If your MCU's SPI peripheral tops out at 104 MHz, the part still runs at that lower speed without issue — the 133 MHz rating gives margin for signal-integrity loss across a long PCB trace or a connector.
Package and footprint — 8-WSON with exposed pad
The pad is electrically connected to ground — tie it to the PCB ground plane with at least four vias. The body is 5 mm by 6 mm, so it fits a compact layout without crowding the decoupling caps.