128 Mbit NOR Flash for automotive code storage
It uses a SPI interface with Quad I/O and QPI support, clocked at 133 MHz, which gives the read bandwidth needed for execute-in-place firmware and fast boot sequences in engine control units, transmission controllers, and ADAS modules. The memory is organized as 16M x 8 bits and operates from a 2.7V to 3.6V supply.
The 133 MHz clock rate with Quad I/O delivers sustained read throughput that keeps the CPU fed without wait states for most automotive MCUs. The QPI mode reduces the command overhead on the bus, which matters when the Flash shares the SPI bus with other peripherals. The interface is backward-compatible with standard SPI, so a legacy controller can still talk to it in single-bit mode while a newer one switches to quad for the performance gain.
Temperature grade and AEC-Q100 qualification
For a design targeting a passenger vehicle or commercial truck, this qualification is the baseline requirement; the commercial-grade FL-L sibling without the A suffix would not be accepted in a PPAP submission.
The 8-SOIC footprint is common across many SPI NOR Flash parts, so a board layout for a 128 Mbit or 64 Mbit FL-L device in the same package should accept this part without a spin.
If you are qualifying this part for a new design, the active status and AEC-Q100 grade give confidence the supply will hold through the product lifecycle.