It communicates over a SPI interface that supports Quad I/O and QPI protocols, clocking at up to 133 MHz. Typical applications include code shadowing in embedded systems, firmware storage for MCUs and FPGAs, and data logging in industrial control, telecom infrastructure, and IoT edge nodes.
133 MHz clock and Quad I/O — what the throughput means for the bus
At 133 MHz with Quad I/O, the S25FL128LAGMFI010 delivers a sustained read throughput that keeps a Cortex-M or RISC-V core fed during execute-in-place (XIP) boot without stalling for wait states. The QPI mode reduces command overhead by operating the bus in quad-wide mode for both address and data, which tightens the latency for random-read workloads. For designs that shadow code to RAM at power-up, the 133 MHz clock means the copy completes in under a second for a typical 1 MB firmware image.
It is ROHS3 compliant.