64 Mbit automotive NOR Flash with Quad SPI
It stores 8M x 8 bits of non-volatile data and code, organized in a uniform 4 KB and 64 KB sector architecture typical of this family. The SPI interface supports Quad I/O and QPI modes at a clock frequency of 108 MHz, giving read throughput suitable for execute-in-place firmware and fast boot sequences in engine control units, ADAS modules, and body electronics.
The 108 MHz clock rate with Quad I/O translates to a sustained read bandwidth of roughly 54 MB/s in quad mode (four data lines at 108 MHz). That is enough to feed a Cortex-M7 or similar core without wait-state stalls during code shadowing. If your design uses single-SPI or dual-SPI, the same clock still applies, but throughput drops proportionally. The QPI mode reduces command overhead by using the same four lines for address and data, which helps in random-read workloads like parameter tables.
Supply range and interface compatibility
The SPI Quad I/O interface is backward-compatible with single-SPI controllers; you can drop this into a legacy 8-pin SOIC footprint if the PCB has the extra four signal traces routed.
No LTB risk to budget for the foreseeable production window.