64 Mbit NOR Flash with 108 MHz Quad SPI — what it delivers
It communicates over a SPI bus with Quad I/O and QPI support, pushing the clock to 108 MHz for fast read throughput.
At 108 MHz in Quad I/O mode, the part delivers a sustained read throughput that keeps a Cortex-M or RISC-V core fed during execute-in-place (XIP) boot without stalling for wait states. The QPI mode reduces the command overhead by switching the entire interface to a quad protocol after the initial instruction, which matters when the bus is shared with other SPI peripherals.
The 16-SOIC supplier device package is compatible with existing layouts for 64 Mbit SPI Flash from other vendors, easing second-sourcing.
It is ROHS3 compliant.