It communicates over a SPI bus with Quad I/O support, pushing the read clock to 104 MHz — enough to feed an execute-in-place (XIP) MCU without a separate DRAM cache.
That means new builds cannot rely on factory orders — the only channel is surplus and broker inventory. No LTB window remains, so any available units are already in the channel.
104 MHz Quad I/O — read throughput without a cache
The Quad I/O interface lets the host read four bits per clock cycle, so the effective throughput at 104 MHz is well above what a single-bit SPI can deliver. That matters when the MCU executes code directly from Flash — the bus can keep the instruction pipeline fed without wait states, as long as the controller's Quad SPI peripheral matches the timing. The 5 µs page write time and 3 ms sector erase (word, page) are typical for this NOR generation; the endurance and retention specs follow the FL-P family baseline.
Package and footprint — 8-USON (5x6) exposed pad
The device comes in an 8-UDFN with exposed pad (supplier package 8-USON, 5x6 mm). Surface-mount only.