Dual N-channel logic-level MOSFET in a 2x2 PQFN
The logic-level gate threshold (Vgs(th) max 1.1 V at 10 µA) lets the MOSFET turn on fully from a 2.5 V or 3.3 V logic rail — no separate gate driver needed for most microcontroller or FPGA outputs.
Conduction loss and switching speed for the BOM
The 45 mOhm Rds(on) at 4.5 V gate drive sets the conduction loss floor — at 3.4 A the drop is about 150 mV per channel. Total gate charge is 3.1 nC at 4.5 V, which keeps switching losses low even at several hundred kHz; a 3.3 V GPIO sourcing a few mA can drive the gate directly. Input capacitance Ciss is 310 pF at 10 V drain bias — the gate drive sees a light capacitive load, so rise/fall times stay under 10 ns with a modest source impedance. The 1.5 W package power limit (6-PQFN, 2x2 mm) means the total dissipation across both channels must stay within that ceiling; a 4-layer board with thermal vias under the exposed pad helps pull heat into the inner planes.
Temperature range and deployment environments
The wide range also covers cold-start conditions in battery-powered equipment.
It is ROHS3 compliant.