The maximum on-resistance of 17.9 mOhm at 8.1 A drain current with a 4.5 V gate drive is the parametric that sets the conduction loss budget. At 8.1 A, the I²R loss is under 1.2 W per channel, but the total package dissipation is limited to 2 W — so both channels cannot run at full current simultaneously without exceeding the thermal limit. The 8-SOIC footprint with standard 0.050-inch pitch demands a 2-ounce copper pour on the drain pads to keep the junction temperature inside the -55°C to 150°C operating range. Gate charge is 11 nC max at 4.5 V, and input capacitance is 1020 pF at 25 V drain-source. These numbers are moderate — a 100 kHz switching frequency draws about 1.1 mA from the gate driver, well within the capability of an MCU GPIO pin if a series resistor limits the peak current. The 8-SO package's thermal resistance to ambient is around 120 °C/W on a standard FR4 board; the 2 W power limit assumes the copper area recommended in the datasheet layout note.
Active production, ROHS3 compliant
No official second-source or cross-reference is listed in the manufacturer documentation, so dual-sourcing requires qualifying a functionally similar logic-level dual N-channel MOSFET in the same 8-SO footprint.