1.85 mOhm at 50 A — the conduction-loss floor
The dual current rating tells the real story: 35 A continuous at 25 °C ambient (Ta) is the board-level limit, while 100 A at case temperature (Tc) is the silicon limit with adequate heatsinking. A designer working a 60 A rail needs the Tc rating and a thermal plan — the Ta number alone undersells what the die can deliver.
Gate charge and switching budget
Total gate charge is 77 nC at Vgs = 10 V. Input capacitance Ciss is 5114 pF at Vds = 15 V. That capacitance, together with the gate charge, defines the driver's switching loss component and the crossover distortion in a synchronous rectifier application.
Package and thermal interface
The part comes in an 8-lead PowerVDFN package — the supplier device package is PQFN 5x6 mm single die. The exposed pad on the bottom is the main thermal path; the PCB copper area under the pad and the number of thermal vias set the junction-to-ambient thermal resistance. The datasheet's 3.6 W (Ta) vs 110 W (Tc) power dissipation numbers bracket the range from a minimal copper layout to a properly heatsinked design. Surface-mount assembly with a standard lead-free reflow profile works; the package is compatible with ROHS3-compliant solder processes.