Dual P-Channel 55V 3.4A — load-switch and battery-protection fit
The logic-level gate threshold (1V max at 250µA) allows direct drive from 3.3V or 5V logic rails, eliminating the need for a separate gate-driver stage in many designs.
105mOhm Rds(on) — conduction loss and thermal budget
At 3.4A and 105mOhm, the conduction loss per channel is about 1.2W at 25°C junction. With the package rated for 2W total power dissipation, both channels conducting near full current simultaneously will push the die temperature toward the 150°C maximum junction rating. The SO-8 copper pad area under the die sets the thermal resistance to ambient; a solid ground-plane pour on the PCB is expected for sustained operation above 1A per channel.
Logic-level gate — direct GPIO drive
The 1V maximum gate threshold at 250µA means the MOSFET is fully enhanced with a 3.3V gate drive. The 38nC total gate charge at 10V gives the switching energy — a 3.3V GPIO sourcing a few milliamps will switch the gate in the microsecond range. For higher-frequency PWM (above 10 kHz), a dedicated gate-driver IC with higher peak current is recommended to reduce switching losses.
It is ROHS3 compliant.