Automotive dual FET — what the 60 V / 20 A rating means for the load
AEC-Q101 qualification and a -55°C to 175°C junction temperature range place it in the automotive power-train and body-electronics tier.
The 53 nC total gate charge at 10 V means a 1 A gate-driver IC can turn the FET on in roughly 53 ns; a weaker driver (e.g. 0.5 A) extends the switching edge and increases crossover loss.
Package and footprint — PG-TDSON-8-10 with wettable flank
The 8-PowerVDFN package (PG-TDSON-8-10 supplier code) is a surface-mount dual-FET package with a wettable flank option — the flank allows automated optical inspection (AOI) of the solder joint on the side of the package, which is a requirement in many automotive assembly lines. The dual configuration shares a common drain pad; the two gate-source pairs are independent. Confirm the pin assignment against the layout before committing the BOM position.
Lifecycle and compliance
The AEC-Q101 qualification is documented, which satisfies the PPAP submission requirement for most tier-one automotive programs.
