Clock distribution with zero added delay
The IMIZ9972BAT is a PLL-based Zero Delay Buffer from Infineon Technologies, designed to regenerate a clock output from a crystal input with near-zero propagation skew between input and output edges. It accepts a crystal on the input side and delivers up to 13 clock outputs from a single reference, with a maximum operating frequency of 125 MHz. The 2:13 input-to-output ratio means you can fan out one crystal reference to thirteen clock loads without adding external buffers — useful for synchronising multiple FPGAs, ADCs, or Ethernet PHYs on a single board.
Supply rails and temperature range
The device operates from a 2.97V to 3.63V core supply, with a separate 2.9V to 3.6V rail for the output buffers — a split-rail architecture that lets the core run at a clean 3.3V while the outputs can swing at a slightly lower voltage if the downstream logic requires it.
Package and footprint reality
Housed in a 52-LQFP (10x10 mm body), the IMIZ9972BAT is a surface-mount part that requires a standard reflow profile. The 0.65 mm pitch is manageable on a 4-layer board; two-layer designs can route the outer rows but will struggle with the inner power and ground pins.
Lifecycle and sourcing posture
This is a current-production part, so you can commit it to a new BOM without worrying about a sudden obsolescence-driven redesign. Note that the part is listed as RoHS non-compliant. If your assembly line or end-market requires RoHS compliance, you will need to verify the date-code or look for a lead-free suffix variant.