650 V SiC Schottky — zero-recovery switching for PFC and flyback stages
Its zero reverse recovery time (0 ns trr) eliminates the switching losses that plague silicon ultrafast diodes in hard-switched topologies — a direct efficiency gain for power-factor-correction (PFC) boost stages, flyback converters, and solar inverter freewheeling paths.
With trr = 0 ns, the IDH04G65C6XKSA1 generates no reverse-recovery charge. In a 100 kHz PFC boost, this eliminates the turn-on loss spike in the MOSFET and reduces the EMI signature from the diode snap-off. The 14 µA reverse leakage at 420 V (25 °C) is typical for a 650 V SiC Schottky of this die size; leakage doubles with temperature, so the thermal design should budget for the hot-case leakage at the 175 °C limit. The 205 pF junction capacitance at 1 V bias is the dominant contributor to the diode's capacitive turn-on loss at high frequency. For a 200 kHz LLC converter, the Coss-related loss is roughly 0.5 W — a figure that should be included in the heatsink calculation alongside the forward conduction loss.
Active production, ROHS3, and sourcing posture
It is ROHS3 compliant. The TO-220-2 through-hole package (PG-TO220-2) is a standard footprint for board-level power stages.