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Infineon Technologies CY9BF112NPMC-G-JNE2 — Microcontrollers & Processors (MCU / MPU / DSP)

Infineon CY9BF112NPMC-G-JNE2 MCU, ARM Cortex-M3, 144MHz

MPNCY9BF112NPMC-G-JNE2
End of Life

Infineon Technologies FM3 MB9B110R series ARM Cortex-M3 32-bit MCU, CY9BF112NPMC-G-JNE2, 144MHz, 160KB Flash, 16K x 8 RAM, 100-LQFP, Tray.

$10.58Ref. price · indicative, final on quote
Packaging100-LQFP
StockContact for availability
Lead timeIn Stock wk
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Specifications

CY9BF112NPMC-G-JNE2 Technical Specifications
ParameterValue
SeriesFM3 MB9B110R
Mounting typeSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))2.7V ~ 5.5V
Operating temperature-40°C ~ 85°C (TA)
Speed144MHz
PackageTray
RAM size16K x 8
Core size32-Bit Single-Core
PeripheralsDMA, LVD, POR, PWM, WDT
ConnectivityCSIO, EBI/EMI, I²C, LINbus, UART/USART
Number of i (O)83
Core processorARM® Cortex®-M3
Case100-LQFP
Data convertersA/D 16x12b
Program memory size160KB (160K x 8)

Product details

ARM Cortex-M3 at 144 MHz with 160 KB on-chip flash

The CY9BF112NPMC-G-JNE2 is an Infineon FM3 MB9B110R series microcontroller built around a 32-bit ARM Cortex-M3 core running at 144 MHz. This puts it in the mid-range performance tier for Cortex-M3 parts — enough throughput for sensor fusion, motor control loops, or industrial protocol stacks without needing an external memory bus for code. Program memory is 160 KB of on-chip flash, backed by 16K x 8 SRAM. For a typical industrial control application — say, a fieldbus node running a Modbus RTU stack with a few PID loops — that leaves comfortable headroom for the application heap and stack after the HAL and RTOS footprint.

Peripheral set and I/O count

On-chip peripherals include DMA, LVD, POR, PWM, and WDT — the usual complement for autonomous operation without external watchdog or supervisor ICs. Connectivity covers CSIO, EBI/EMI, I²C, LINbus, and UART/USART, giving the designer a choice of serial buses for sensor interfaces, display modules, or legacy fieldbus adapters. 83 general-purpose I/O are brought out to the 100-LQFP package (14x14 mm body). That is a dense pin count for a 100-pin QFP — expect that most of the peripheral muxing shares pins with GPIO, so the actual usable I/O count depends on which serial interfaces are enabled.

Frequently asked questions

What compliance documentation does Infineon provide for the CY9BF112NPMC-G-JNE2?

The part is ROHS3 compliant per the manufacturer's declaration. Standard Infineon documentation includes the datasheet, application notes, and a PCN subscription channel for any changes to the active lifecycle status.