The CY8C5867LTI-LP025: This is a design-in viable part, not a shortage-era scavenge. The PSoC 5 toolchain and SDK are mature; the part ships in tray packaging and the 68-QFN footprint is standard across the CY8C58LP family.
67 MHz Cortex-M3 with 128 KB flash — memory budget check
The ARM Cortex-M3 core runs at 67 MHz — enough for a capacitive-touch HMI polling at 100 Hz while the DMA engine moves ADC results into SRAM without CPU intervention. The 128 KB flash holds the application binary plus a bootloader; the 32 KB SRAM leaves roughly 12-16 KB for the stack and heap after the HAL and a small RTOS footprint. The 2 KB EEPROM stores calibration constants and failsafe parameters without wearing the flash sectors.
20-bit ADC and CapSense — analog front-end for sensor fusion
The data converter block includes a 20-bit delta-sigma ADC and a separate 12-bit SAR ADC — the 20-bit channel handles precision strain-gauge or thermocouple inputs, while the 12-bit SAR scans multiple analog channels at higher throughput. Four 8-bit DACs provide analog set-points or waveform generation. The CapSense peripheral implements self- and mutual-capacitance touch sensing without an external touch controller; the DMA engine streams the raw counts to SRAM for post-processing. The 38 general-purpose I/O include the CapSense shield electrode and the LCD segment drive — the LCD controller drives up to 4 commons and 32 segments directly.
PSoC 5 vs PSoC 6 — what the Cortex-M4 peer changes
The CY8C6137BZI-F54 runs a Cortex-M4 at 150 MHz with 104 I/O and a 1.7 V supply — it is not a pin-drop replacement. The 68-QFN footprint of the CY8C5867LTI-LP025 does not map to the PSoC 6's 124-ball BGA; a board spin is required. For a BOM that already qualifies the CY8C5867LTI-LP025, the Cortex-M3 part remains the correct fit unless the application needs the M4's DSP extension or the higher I/O count.