PSoC 4 CY8C4125FNI-S433T: 32-bit ARM Cortex-M0+ with integrated CapSense and mixed-signal
Includes on-chip CapSense block for capacitive touch sensing, plus a mixed-signal front end with 16-channel 10-bit slope and 16-channel 12-bit SAR ADCs and two IDACs. Typical applications span touch-button or slider interfaces on appliances, industrial control panels, medical user-input devices, and IoT edge nodes that need to read multiple analog sensors and communicate over I2C, SPI, UART, or LIN bus.
The 24 MHz Cortex-M0+ core is not a number-cruncher; it is a control-loop and state-machine engine. At this clock speed, the flash can run with zero wait states, keeping interrupt latency predictable for real-time sensor polling. The 1.71 V minimum supply voltage lets it operate directly from a single lithium cell or a 1.8 V rail, which simplifies the power tree in battery-powered designs — no separate 3.3 V regulator needed. The 32 KB Flash and 31 I/O in a 35-bump WLCSP mean this part is sized for a specific tier: enough memory for a modest firmware stack with CapSense tuning tables and communication buffers, but not intended for large application code or extensive data logging. The WLCSP package requires careful board-level assembly planning — it is a direct-chip-attach footprint, not a hand-solderable QFP.
Mixed-signal on a single chip: 16-channel ADC and dual IDAC
The part carries both a 16-channel 10-bit slope ADC and a 16-channel 12-bit SAR ADC. The slope converter is useful for low-frequency measurements like temperature or battery voltage where noise rejection matters; the SAR ADC handles faster signals up to the 12-bit resolution. Two IDACs on the output side can drive sensor excitation currents or generate analog reference levels, eliminating external DACs in many sensor-front-end designs.