24 MHz Cortex-M0+ with on-chip CapSense
The CY8C4025FNI-S402T: This core delivers enough throughput for sensor polling, UI control, and communication protocol handling in a single chip. On-chip peripherals include CapSense touch sensing, LCD drive, PWM, and a brown-out detect/reset — the CapSense block alone can replace a separate touch controller in human-interface applications like capacitive buttons or sliders. The 32 KB flash and 4 KB RAM (4K x 8) set the firmware budget: the flash holds the application code and constant data, while the RAM handles stack, heap, and small buffers. For designs needing more than a few kilobytes of runtime data, plan for external memory or a higher-tier PSOC 4 variant.
WLCSP package and board integration
The 25-WLCSP package (2.02 x 1.93 mm) is a wafer-level chip-scale package with solder balls directly on the die — no molded body. This shrinks the footprint to the bare die size, which helps in space-constrained designs like wearables or sensor modules, but the 0.4 mm ball pitch demands careful PCB layout with via-in-pad or microvia fan-out. The wide range means a single regulator can feed the MCU without a secondary LDO, simplifying the power tree.
Connectivity and I/O budget
The I²C and SPI interfaces allow daisy-chaining sensors or EEPROMs, while the UART handles debug or fieldbus bridging. The single 10-bit ADC limits analog input channels — if the application needs more than one analog sensor, an external analog mux or a PSOC 4 part with more ADC channels (like the CY8C4245LQI-483 with 8x12-bit) is the migration path.
ROHS3 compliant, meeting the latest EU restriction-of-hazardous-substances directive. No additional compliance documentation (REACH, UL, IEC) is listed in the available records.