The Cypress CY7C429-10JC is a 18K (2K x 9) asynchronous FIFO memory in a 32-PLCC (J-lead) package. It offers a 10 ns access time and supports a 50 MHz data rate on a 4.5 V to 5.5 V supply. The part includes retransmit capability and supports depth and width expansion for building larger buffer arrays.
The 10 ns access time leaves 10 ns for address setup and data hold at 50 MHz.
No official successor is listed.
Memory organization and expansion
The 2K x 9 organization provides 18 Kbit of storage with a ninth bit that can be used for parity or a control flag. Depth expansion cascades multiple devices to increase the word count; width expansion combines them to widen the data bus. The retransmit capability allows the FIFO to re-read data without a full reset — useful in packet retry or error-recovery sequences.
The 32-PLCC (J-lead) package is surface-mount with a 11.43 x 13.97 mm body. J-leads offer good solder-joint inspection access but require a PLCC socket for prototyping or rework.