The Cypress CY7C4261-10JC is a synchronous FIFO memory in the CY7C series, organized 16 K x 9 bits (144 Kbit total). It clocks at 100 MHz with an 8 ns access time, meaning the read data appears on the bus within one clock cycle of the read enable — no wait states needed at that speed for most glue logic. The 9-bit width accommodates an extra parity or tag bit alongside an 8-bit data byte, a common requirement in telecom framers and data acquisition buffers. It supports depth and width expansion, so multiple devices can cascade for larger buffers without external arbitration logic. Programmable flags are available for almost-full/almost-empty thresholds, giving the system designer control over flow control hysteresis.
32-PLCC footprint and commercial temperature range
Housed in a 32-lead PLCC with J-leads (supplier package 32-PLCC, 11.43 x 13.97 mm body), this is a surface-mount package that can also be socketed for prototyping or field upgrades.
This means the part is no longer manufactured and is not available through franchised distribution channels. We can quote the CY7C4261-10JC against an RFQ, confirming availability and current pricing at quote time.